1. Field
Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a substrate by a chemical mechanical polishing process.
2. Description of the Related Art
A three-dimensional (3-D) integrated circuit is a single integrated circuit built by stacking silicon substrates and/or dies and interconnecting them vertically so that they behave as a single device. Vias have been used in 3-D integrated circuit fabrication to provide electrical coupling between one or more layers of conductive material. More recently, through-silicon vias (TSV) have arisen as an alternative method to conventional wire bonding. TSV structures allow for shorter interconnects by forming interconnects in the z-axis. The interconnects may be created through a substrate by forming vias extending from a front surface to a back surface of the substrate. After creating the interconnects in the z-axis, multiple substrates can then be stacked on top of one another, and electrically coupled through the vertically extending interconnect. TSV structures provide a means for reducing the footprint of substrates in semiconductor applications.
TSV structures are formed using sequential material deposition and material removal techniques on a substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing.
Planarization or “polishing” is a process in which material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material, removing undesired surface topography, and surface defects, such as surface roughness, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent photolithography and other semiconductor manufacturing processes.
Chemical Mechanical Planarization or Chemical Mechanical Polishing (CMP) is a common technique used to planarize substrates. CMP utilizes a chemical composition, such as slurries or other fluid medium, for selective removal of materials from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, thereby pressing the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus affects polishing or rubbing movements between the surface of the substrate and the polishing pad while dispersing a polishing slurry or solution to affect chemical and mechanical activities and consequential removal of materials from the surface of the substrate.
One objective of CMP is to remove a predictable amount of material at a high removal rate while achieving uniform surface topography both within each substrate and from substrate to substrate when performing a batch polishing process. The high removal rate of material is often achieved through the use of expensive polishing slurries and the application of high polishing pressures to the structure being polished. However, such high polishing pressures may lead to damage of the underlying structure. Further, the use of expensive slurries contributes to an increased cost of ownership.
Therefore, there is a need for a low cost polishing process which accurately and reliably removes a predictable amount of material at low or no pressure while achieving uniform surface topography at higher removal rates.